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Engineering - Memory  1. Introduction Rotating Drum memories were the ERA entree into the computer world in that programs could be loaded and saved when power was removed. These provided the technology baseline which eventually led to all rotating magnetic memories - including the PC hard drives. Even as the magnetic media and sensors were replaced with optical readers and media to create today's PC CDs, the rotation mechanisms and sensor proximities grew out of the ERA magnetic drum patents. |  On this page, scroll down to:Introduction [left] Drum Memories Braided Wire Memory Plated Wire Memory Bubble Memory Others (core and film)
 In the 80's, the original 1832 AN/AYK-10 computer's film memory was replaced with semi-conductor memory chassis - that too needs documenting. [lab] Thanks to Jim Howe, Larry Bolton, and Gary Hokenson for their recollections of Memory developments. [lab] | 2. Drum Memories  The drum development engineers and management shown in this early 50's photo, left to right are:
William Keye, Arnold Hendrickson, Robert Perking, Frank Mullaney, Dr. Arnold Cohen, and John (Jack) Hill. We'd claim that this drum was the world's first computer 'hard drive'. The rotating drum technology allowed ERA to deliver the world's first production stored-program computer* (ATLAS - ERA 1101) to a customer site in October 1950. The engineers making the installation deliver to the National Security Agency predecessor were Frank Mullaney and Jack Hill. As shown in the photo above, these Drum products came in various sizes. They were first used in several classified processors, then in the early 1100 computer series and the UNIVAC SS-80 and SS-90 computers. Dr. Cohen and Sid Rubens are credited with patenting the rotating magnetic drum. On the right is the installation of a drum into an early 110x computer. *The ENIAC was modified in the spring of 1948, thus demonstrating stored-program concepts1 with a new control section. This was a couple of months before the British Manchester Baby that first ran a small demonstration program in June 1948. It was also before the BINAC in 1949. Each of these early 'stored-program' machines was a one of a kind laboratory unit which used various volatile memory storage sections such as mercury acustic delay lines. From a functional standpoint, these early memory technologies were akin to today's PC Random Access Memory - the contents are lost when power is turned off! The magnetic drum memory machines kept (stored) their programs when power was turned off, therefore did not have to be re-loaded time and again. The ERA ATLAS delivered into a customer's facility started the 1100 production series of commercial computers traceable to the UNISYS 2000 computers of today. [LABenson] 1. IEEE Annals of the History of Computing - Volume 29, Number 4. 'ENIAC as a Stored-Program Computer: A New Look at the Old Records' by Crisin Rope.
3. Braided Wire Memory by Jim Howe
I believe that the "braided wire memory" was also known as the "Rope" memory. This memory was an sort of an early PROM (~1966-1968), and was a configured as either 30 or 32 bits (depending on the application). 256 or 512 words - this memory type served as the boot-strap memory for the CP901 (original PC-3 aircraft computer) and also for the original AN/UYK 7 computer. The module was about ~4" x ~4" x ~0.6". The memory consisted of 30 or 32 ferrite cores (one core for each bit position), and either 256 or 512 magnet wires arranged in a diode selection matrix, one wire for each word location.
Each of the ferrite cores had about 30 turns of wire on it connected to the base-emitter of a NPN transistor. A current pulse was driven down one wire to read the data on that particular "word line". If the wire went through the one of the cores, the corresponding transistor would turn ON, and that bit would be read out as a "1". If the wire bypassed a core, the transistor would remain off and that bit would be read as a "0". A loom was made to string (i.e., program) the rope memory (the cores were physically moved up or down to make "0's" or "1's" as the individual word lines were pushed in a straight line through the mass of wires in the "rope"). The individual word line wires in the rope were terminated on printed circuit boards inside of the rope module. [jh]
{Editor's Notes: Jim Howe's 'mechanical description' is quite accurate. The wires going through or around the cores were about 40 gauge wire. 512 of these wires did look like a braided rope. I can vaguely remember manually re-stringing a couple of word line wires to fix a problem with an initial program. Sub-routines within the core-rope had to have special entrance and exit method because the usual RJP (return jump mnemonic) instruction could store the 'came from' address as it usually did in core memory.
I had not equated the term 'braided wire' memory with the 'core rope' memory which was used in the CP-901. The CP-901 had 512 words, not 256. These 512 words contained a paper tape bootstrap for diagnostic/test program loading, an operational drum or magnetic tape loader, and a built in self test program. I wrote the paper tape loader, I believe that Jim Halvorson did most of the self test programming, don't recall who wrote the mag-tape and drum loader. There was an original version for software development lab use then a production version for use aboard the P3C system. The diagnostic program did a basic ISA check, an arithmetic section check, a registers test, a simple bank 1 core memory test, then an output/input test using a jumper cable from an output channel to input channel 6. If all of these tests completed ok, about 90% of the CPU was functioning, 25% of the core memory, and 1/16th of the I/O. If all of these core rope tests completed, it was possible to load from magnetic tape/drum to load a more exhaustive set of tests.
When we did developed the 1830B for the German Navy's Fast Patrol Boat program, the core rope program was updated to load from the 1840 Magnetic Tape Unit. The designed in diagnostic program was tweaked for the other minor design changes from the CP-901.} [lab]]
4. Plated Wire Memory by Larry Bolton, Clint Crosby, and Jim Howe
5. Bubble Memory by Lowell Benson
Bubble Memory devices were sort of a competitor with the MNOS devices being manufactured in our Eagan Semi-conductor plant. Those MNOS devices were being used on an Air Force project - perhaps Jim Inda could recall which.
Our first non-IRAD use of Bubble Memory devices was an experimental full ATR unit which was built for the Naval Air Development Center at Johnsville, PA.. Roman Fedorak was the Government technology sponsor and project monitor. Ray Hedin and Sam Meddaugh working for, then department manager, Dennis Amundson were the engineering personnel on the project. Roy Lecy was the Program Manager for NADC projects at that time. The intent of this Government sponsored project was trying to find a solid state replacement for the drum memories operating aboard the P3C and S3A aircraft in their ASW systems.  The souvenir mug shown here illustrates the ATR implementation on the right. The left picture on the mug is the Coast Guard implementation, a chassis modified from the AN/UYK-20 computer.
It was the NADC design baseline that won a contract with the Coast Guard to provide a mass memory storage device for their patrol boats which were beginning to implement a AN/UYK-20 Command and Control System.  The initial component used was the Motorola 1-megabit device show at the right. There were a lot of quality control concerns during the first ten units as Motorola struggled with their component manufacturing processes. For the Coast Guard program, we delivered 26 units over a two year period. Each unit had 16 array boards, each with eight devices. Ray Hedin was the lead design engineer and checkout person for the first three units as the build was transitioned from the Plant 8 prototype shop to Plant 1 manufacturing. P/N 7917502 4-megabit bubble memory device specification for components made by Hitachi eventually replaced the initial 1 Mbit Bubble Memory (chip) components In June of 1984, Lowell Benson transferred from design engineering to Program Management to head-up the Coast Guard project. Shortly thereafter there was a PM re-organization in which I reported to Marv Mirsch who was Director of Special Products. As the CG project was wrapping up, I took on PM responsibility for the CIA's RISC chip development project reporting to Neil Hahn.
 6. Others 6.1 Core Memory At the right is a 4k (4,096) bit memory plane. Initial planes like this had 2,048 cores in each half (window) of the support structure. There were four wires laced through each core, the X and Y address lines, a sense line, and an inhibit line. This basic structure was used for the 642A, 642B, 1218s, 1219s and other computers up to the CP-901 computer. Beginning with the the AN/UYK-8, CP-890, and AN/UYK-7 the designs went to a single support window allowing the cores to be closer together thus facilitating a faster read and write time. The other key was that these systems used a three wire system. the X and Y address lines and a third wire used as the sense line during the read half cycle or the inhibit line during the write half cycle. The UYK-8 and UYK-7 projects stacked 32 planes to make up their core stack. The CP-890 was able to operate at a very conservative 1.8 microsecond cycle time. The UYK-7 and UYK-8 ran at a 1.5 microsecond cycle time. The 1830B German Navy computer also used these core stacks, continuing to operate at the 2 microsecond cycle time of the CP-901 processor. By the time we were developing the 16 bit computer line, we started to purchase core memories in a 6"x9"x1" module from several vendors. [lab] 6.2 Thin Film Memory  Shown below are three of the thin film layers that were used to make up a plane. With film memory, we were able to engineer a 32k word by 32-bits chassis which fitted into the same space as a 16k word core chassis. Our initial use of film memory was for the 20B computer which had about 128 30 bit words, mapped onto the lower memory and used for the Input/Output buffers and the real time clock. The 1832 (An/AYK-10) computer designed for the S3A aircraft used film memory exclusively for 12 years, then was replaced with semiconductor units as the technology reached end of life conditions. (I'd sure like to get someone who knows about this to write a bit for us!) [lab] 6.3 Semi-conductor Memory
VIP Page 45 updated Sunday, March 30, 2008 |
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