3. Computer Descriptions
3.1 AN/UYK-7 - project started April 1968, first delivery 4/21/1969.
The AN/UYK-7 standard shipboard computer was designed in accordance with stringent military specifications as to performance and ruggedness. It was in use throughout the U.S. Navy.
The AN/UYK-7 became the heart of the second generation NTDS system, replacing the aging 20Bs while implementing an architecture capable of supporting multiple I/O controllers and having multiple processors sharing memory and software tasks. Innovations in this design are numerous, i.e. an eight port memory that allowed three processors and two I/O controllers to be accessing memory concurrently as long as the memory Sources were to different memory banks. The first enhancement to the AN/UYK-7 was the implementation of a film memory chassis which created a 32k word memory in the same volume as the initial 16-k core memory chassis. The film memory technology was adapted from the AN/AYK-10's memory design. Each memory chassis had eight memory buses. In a multi-processor configuration; three instruction fetches, three operand fetches, and two I/O word transfers could take place simultaneous if all were referencing different memory banks.
The UYK-7 design used the heat sink, T-bar card design and heat exchanger design from the CP-901. The integrated circuit flat packages were mounted onto a conductor which carried chip heat to the T-bar at the top. When inserted into chassis, a heat exchanger plate was clamped to the chassis. Air forced through the heat exchanger cooled the unit. The typical operating temperature of components on this card type was 30 degrees above ambient.
The lead logic designer from the CP-901, Ken Oehlers also became the lead processor designer for the UYK-7. John Bonnes also joined the design team for this computer as the CP-901 checkout lead was taken over by Lowell Benson. [lab]
The UYK-7 was succeeded on 688 fast attack submarines, Trident submarines, and surface ships by the standard shipboard computers, the AN/UYK-43 and -44. These provided computing power for the U.S. Navy for decades.
A common executive program facilitated operational programming. [lab]
Comments From: Rick Orozco via web site on 23 January, 2009.
Hi, Thank you for the interesting web site. I was a UYK-7 computer tech for the US Navy from 1989-2000. I enjoyed learning the system inside and out and was a fairly good programmer in machine language. On the USS John Rodgers DD-983, we had a "spare" stand alone bay, which I actually wrote about a 10,000 line word processing program for use at our teletype. Of course this was right before the introduction of the PC, so it came in handy.
I also worked on the CP-642 when stationed onboard the USS Midway CV-41. In fact, in the picture of the SINS computer on your web site, you can still see my notes for reloading the computer, the little white index card posted on the control panel. {Editor's note: see section 3.6 of Computers, 30-bit.} Thanks to the many great engineers and programmers that created these systems and helped to make our military the best in the world.
Rick Orozco, Chief Data Systems Technician, US Navy Retired
3.2 Unisys Type 1832, AN/AYK-10 - Also called the S3A computer.
This project started in 1969 with first delivery September 14, 1970. The AN/AYK-10 is a dual processor, dual I/O controller airborne version of the UYK-7 ISA with special I/O used for ASW missions aboard the Lockheed S3A carrier based aircraft. Innovations of this design: 1) dual mated film memory chassis running at 1.5 microseconds - each with 6 access ports. 2) a dual processor design interconnected so that if one CPU or one memory chassis or one I/O chassis failed, the system would continue to operate in a reduced capacity mode. Thus a reduced flight mission could continue - maybe just track 3 sono-buoys instead of 6 to 8, etc. 3) a unique frame design that fit at the rear of the S3A crew compartment - the wheels folded up almost against the sides of the Power Supply and third memory drawer.
Don Mager was the project engineer, Gary Bosworth and Gerry Shaw were two of the design engineers on this project. The operational software was developed by Sperry at the Valencia operations building. The first computer was delivered on 9/14/1970. There were a total of 205 of these computers built, including those for the CP-140. [lab]
Photo submitted by Jim Rapinac. Sperry Univac DSD attendees, L-R present at the first aircraft roll-out were:
Jim Rapinac, General Manager, Special Programs, Salt Lake City
Bill McGowan, Marketing Rep, LA office
Ernie Hams, VP Program Management
Dick Gehring, VP and General Manager
Ken
Oehlers, S-3A Engineering Director
Dan Brophy, S-3A Program Manager
Dewaine Osman, VP Marketing
John Spearing, DSD Valencia Site Manager
Norbert Kielbach, Marketing Rep, LA office
3.3 The CP-140 is the Canadian Patrol aircraft developed for their Aurora program. It is essentially the Canadian version of the P3C for their ASW missions. Instead of the CP-901 computer, it used the Sperry 1832 three memory chassis instead of the two used aboard the US Navy's S3A. The Canadian government nomenclature assigned to this machine was AN/AYK-502, not to be confused with the later AN/UYK-502 shipboard mini-computer.
The Canadians were instrumental in providing funding for the development of a semi-conductor memory chassis for this computer as a replacement for the aging mated film memory. These new memory chassis were manufactured at the Winnipeg facility and sub sequentially back fitted into the S3 airplanes. [lab]
3.4 S3B Systems Computer
The 1832 (AN/AYK-10) enhanced version implemented a doubled capacity semiconductor memory chassis (designed for the AN/AYK-502) to upgrade the original film memory drawers.
The aircraft nomenclature was upgraded to S3B because Sperry Univac also did a design update to the Input/Output Controllers to effect a Harpoon missile launch capability. The four 6" x 6" PC cards weighed just 3 lb. instead of the MacDonald Douglas 40 lb. launch computer used aboard the P3C. The power consumption of this feature was an additional 5 watts compared to the 200 watts on the P3C. 
Gerry Shaw, Gary Bosworth, and I did the technical work on the proposal. Ken Graber and Mark Nelson did most of the logic and electrical design of the launch interface.
Especially tricky was the Failure Modes and Effects Analysis which Mark did. He had to determine how the failure of any component would manifest itself, i.e. not allow the system to launch or accidentily launch the missile. No single component failure could launch! Good job with the design Mark and Ken. [lab]
3.5 AN/UYK-43 - This 32-bit ISA was specified for the emerging UYK-7 replacement, the UYK-43 as the third generation NTDS computer. Won by UNISYS. This unit's innovations included a designed in maintenance processor, cache memory for performance enhancements, and plug-in NATO Serial interface. Most of the logic design was implemented using Gate Array technologies.
Many of the command and control functions are transitioning yet to the Q-70 as a fourth generation NTDS core. [lab]
A bit of irony is that in the early 80s, UYK-7 enhancement studies hired two University of Minnesota professors - Dr. Peter Paton and Dr. Bill Franta - to do cache memory performance studies. They used Fortran software executing on the CDC 1604 to obtain performance results for several cache architecture designs. These studies provided data to help design the AN/UYK-43 system and to solve a subsequent cache memory 'I/O flushing' problem in the commercial 1110 computer series. Lowell Benson was the engineering manager responsible for interfacing with the University. Dave Kaminski was the lead design engineer - he later was one of the UYK-43 design engineers. [lab]
4.0 Memory Processor by Dick Erdrich
I should note here that when I did the Architecture for the Memory Processor to replace the CP-890 I created a design with 24 bits of addressing. We delivered two processors and a common memory rack containing 8 MB in each of the Trident Memory Processors. Two processors could easily share a common memory due to the presence of extremely large Cache Memories in front of both processors. Commercial processors at the time were only using level 1 caches (level 2 was not here yet) of 256 bytes. Each Memory processor CPU had 256K bytes. That was all done in the early 80's. [rae]
Shown here is the engineering development team.
Knealing in front are Dick Erdrich, Joe Dearing, Neil Macrorie, and Stan Dorr. Standing at the left are Bob Litz, John Bergman, and Jim Frazier.
Standing at the right are Paul Rodriguez, Bill Zekoff, Marv Janisch, Jim Hadine, and Mel Janisch. Photo submitted by Jim Frazier.
Memory Processor: The ‘Memory Processor’ was a 32-bit machine that was used to provide real-time navigation data to the Improved Accuracy Program targeting computer in the Trident II Missile system. I designed the architecture based on the type of data needing manipulation and included some unique capabilities not available elsewhere. It looked a little like a greatly expanded 1616 structure with 4 sets of 32 general registers of 32 bits each. The 30 bit CP-890 software could be run by using a cross-compiler written by Sperry Systems Management (SSM). The first demonstration of the memory processor was done running the existing the Trident I navigation Code. The support software was written by SSM and was based on the Pascal Standard. The eventual High Order Language, when certified, was ADA. When I designed the architecture I took classes in ADA usage and noted that the generated code liked to use pointers to the extent that they would often use nested pointers. To allow this to happen without slowing execution down, I created a pipeline for instruction and operand address generation. We had overlapped executions in many of our earlier machines but this was the first time to my knowledge that a three stage pipeline was used.
Each register set was tied to a context state: Hardware, Executive, Supervisory, and Task. Context switching took place by instruction or during an interrupt scan. Being an interrupt driven system I concentrated on keeping context switching time to a minimum. The number of registers was required by the fact that the critical processing was done on complex floating point values with a pair of registers holding the real component and another pair holding the imaginary value. This got even trickier when we went to double length (64-bit) operations. 
These weren't used very often but when concluding the final navigation solution all of those numbers to the right of the decimal point became important. The instruction set included a full suite of trigonometry functions and the indexing was optimized for matrix operations. One of our goals was to complete a 1024 point complex Fast Fourier Transform in under 10 milliseconds.
This is just a sample of what that machine had in it. I could go on for hours talking about the huge memory, the huge cache memory, the first implementation of 1553 serial on a non-airborne platform, the fully programmable I/O configuration capability, etc. But that’s probably for another day.
Cheers, Dick.
Shown here is the checkout and test crew. Helping Lowell (lab) with the face identifications were Dan Reiman (dbr), Dick Lundgren (rfl), Paul Mahowald (pm), and Larry Bolton (lb) - Thanks guys
From left to right they are:
Brent Anderson dbr, Paul Mahowald rfl, Paul Dietzler lab, Brian Newman lb, Paul Rodriguez lab, Greg Berger dbr, Jim Frazier lab, Dan Reiman lab, John Justin dbr, John Bergman dbr [Cecil Metz's brother-in-law lab], Dan Gilbertson dbr, and Dave Smith pm.
VIP Page 55 updated 20 January, 2010