2.0 Genealogy Chart for Air Force Computers.
3. Computer Types
3.1 RMF 400Not obvious on the Genealogy chart below was that the RMF-400 was built as an emulator of the Singer Kerrfot 2070 computer which was originally used aboard the B-1 bomber. [lab]
I was the Northwest marketing rep at the time of the Singer Kearfott emulator. It was initially bid to Boeing Seattle for the original B-1 Program. Boeing felt Singer Kearfott was overcharging them. When Gene Weller, Headquarters Marketing, and I reviewed the requirement with Glen Kregness, Glen's analysis was we needed a board to replicate some of the functions we couldn't address with the MPC technology. Thus was born the "computer adapter board, the efficient method for hardware replication." Boeing engineers loved it and we did win the competitive procurement. Unfortunately the original B-1 program was cancelled and we were not the winner when it was reactivated. [Lyle Franklin]
3.2 WASP The Weasel Attack Signal Processor (WASP) was used aboard the F4-G airplane. [lab]
3.3 B2
Another version of the RMF family is aboard the B2 stealth bomber. This was a classified development until the rollout of the first airplane. Jim Inda was the Project Engineer responsible for development of the computer(s) for this airplane. {Editor's note: Photo found on the internet.}[lab]
3.4 YF-23
The AN/AYK-15A computer implemented the Air Force Mil-Std-1750A Instruction Set Architecture. The AF defined the 1750 ISA in order to bring standards to their system support chaos which had over 300 ISAs in equipments from thirty some vendors. Several variations of this ISA were designed over time. A notable variation was the "Common Module Family" that was built for Northrop for their YF-23. The Department of Defense chose the Lockheed YF-22 as the Advanced Tactical fighter after a fly-off. Model shown at the right from Lowell's memorabilia collection. [lab]
3.5 Joint Strike Fighter (JSF): by Dick Erdrich
The Integrated Core Processor (ICP) subsystem provides critical processing capabilities for the aircraft’s sensors, communications, electronic warfare guidance and control and cockpit displays.
I was involved with the original engineering effort for the F-35 [Joint Strike Fighter] program. We had used an existing processor module from the Owego Division [Old IBM Federal Systems Division] and I had been tasked with the overall processor design which used the module and, after the initial deliveries for software development had been made, was asked to study the possibility of increasing the number of processors on each module for the production program. I did my study and to my surprise management gave the go ahead to build it. It was done on IR&D money so outside interference was not an issue. After an 8 month effort, done mostly as I would have in the old days, the Quad Processor was operational. I used two Freescale [Motorola] processors per module side of an 6" x 9" Printed Wiring Board (PWB) - with all of the usual support hardware - three types of memory, UARTs, E-Nets etc. With all of the decoupling capacitors and transmission line terminators necessary for the high speed stuff I ended up with over 2100 components on the PWB. Two PWB's would be bonded together to make up the module. It was operational the first time around, no artwork changes were necessary. We again let the software development folks use the initial hardware but I got a chance to do it again as now the customer got involved and wanted the very latest processor available for production. I spent a solid month doing the design for the upcoming processor chip and then turned it over to Dave Senechal, Reed Churchward, Charles Grimmner, and Don Degerstrom. They are going through the normal problems of trying to get leading edge components but they will be successful.
After 47 years, 4 months, and 13 days I didn't feel as though I needed to hang around just to watch another processor run. Its' been a heck of a run! Dick
VIP Page 57 updated 23 August, 2008