1830 Phoenix Information:
Customer - AIR FORCE Environment - Airborne First Delivery - July 1966 Quantity built = 3
Vol/Ft3 = ? Wt/Lbs = ? Pwr/Wts = ? Mem/Cyc = 2 usec Mem/Cap = 16 k core
I/O rate = I/O channels 8 duplex; -3v.
3.9 Univac type # 1230 - by Don Mager: (Apollo)
The 1230 computer was developed for NASA, to be used for all telemetry data processing for the Apollo mission. A total of 39 computers were eventually delivered to NASA. We started the design of the 1230 in the fall of 1964 and delivered the first unit July, 1965. Bob Oulicky designed the I/O section, Glen Kregness designed the arithmetic section and Don Mager designed the control section. Although the 1230 was sometimes referred to as the Modified 642B, it was a total new logic design utilizing 642B logic pc cards, 1219 memory components, the first "mated film" memory for the control memory, and it was housed in a standard 642B cabinet. [dvm]
The instruction set was the standard 30 bit repertoire with several new instructions to address the increased memory size. Although the main memory was only twice as fast (2 micro-seconds) versus the 642B's 4 u-sec, the overall performance approached 4 times that of the 642B. This was accomplished by the control section being capable of over lapping instruction and operand fetches to/from the two, 16k each, memory banks. I believe this was the first Univac Defense Systems Division (DSD) computer to have this capability. Another interesting feature was the capability to expand the memory, in an adjacent cabinet, to a maximum of 264k words - the first time we went beyond 32k. Also unique was the asynchronous operation of the external memory versus the synchronous memory operation of all the earlier DSD computers. One of the challenges with the external memory was dealing with the large number of connections without changing the 642B cabinet design. Necessity being the mother of invention, the number of data path wires was reduced by 50% by sending the data bi-directionally over the data paths and I was subsequently granted my first computer related patent* for this method - a technique that today is ubiquitous. [dvm]
As a near term follow on project, we developed the 1230 Expanded Memory Unit, almost an identical box with just memory chassis in it. This was simply called the 1230 EMU.
1230 - CP-855/UYK Information:
Customer - NASA/Navy Environment - Laboratory First Delivery - July 1965 Quantity built = 63
Vol/Ft3 = 60 Wt/Lbs = 2100 Pwr/Wts = 3500 Mem/Cyc = 2 usec Mem/Cap = 131k
I/O rate = 500 kw/sec I/O channels - 16 duplex; 3v or -15v
Software available was: FORTRAN, SYMON, SYCOL, CS-1, and a Service Library
3.10 CP-890 - Univac Type #1836 by Dick Erdrich and Don Mager
The CP-890 was a third generation computer design, it began in July 1966. {Editor's note - First generation used vacuum tubes, second generation used transistors.} What defined this generational step was the use of the Diode Transistor Logic integrated circuits. These were the P/N 7901000 and 7901001 Small Scale Integration flat packs used for all of the logic functions. All of the following computers, until the 1616, used the same basic DTL technology. These included the AN/UYK-8, 1530 Missile Tracking Computer, and the ARTS-III IOP as well as the AN/UYK-7 and AN/AYK-10 [the S-3A mission computer] 32-bit computers. [rae]
Don Mager did the Engineering proposal, was the development project engineer, and managed the team through delivery of the first six units. John Bruder was the key memory engineer - this unit had UNIVAC's first three wire core memory. Neil Macrorie designed the I/O section. Jim Warwick did the mechanical design. The power supply design to meet harsh input power specifications was done by Bob Wyland. Jack Smith reported to Don as Project Engineer of the companion I/O Buffer unit. Ray Dombeck worked on the I/O Buffer design, later was the CP-890 support engineering supervisor. I designed the control memory which originaly was to use the mated-film technology. I became aware that the Minuteman project at Honeywell had developed a 16 bit memory cell. I sought management approval to use it instead of the mated -film. After several arguments among engineering management, Red Phillips intervened to approve use of the 16 bit memory chip. About half way through the design, it became evident that the power consumption would be exceeded. I asked Jack Metzger to determine the impact of running the logic circuits at 5.5 volts instead of the specifiec 6 volts. After an analysis determined that the performance impact would be nil, we set the primary Integrated Circuit voltage at 5.5 volts saving about 20% of the projected logic power - this decision resulted in a cooler and more reliable computer. [dvm]
The CP-890 was specifically designed for SP-24 to replace the NAVDAC that was aboard the Polaris boats. I had been told by Navy folks that the mean up time of the NAVDAC computer very poor. True or not, I don't know. I do know that there was a very strong emphasis on reliability during our design. I ended up by doing virtually all of the CPU design. Leroy Olson was supposed to do the Control section and I was assigned the Arithmetic section as this was the first implementation of a 30-bit floating point hardware algorithm. Leroy had a chance to go into management and bailed out shortly after the project started and I inherited the remainder of the design. Jack Metzger and Mel Wagner did the circuit analysis for all of the logic and I/O modules. The design rules were extremely conservative. It made the job a lot tougher but the end result was a bulletproof design. I did a study for SP-24 after production had started and was able to increase the clock speed by 30% before anything went bad. Of more interest to me was that after I had fixed the limiting logic, a piece of my design in the control section, I was able to increase the clock speed by 55% before a number of things started showing up. The Navy was happy with the results but never gave any thought of increasing the clock speed in the fielded units. They liked the reliability also. [rae]
The CP-890 could operate in normal or expanded addressing modes. The expanded addressing mode was adopted from the the NASA 1230 computer. In normal mode the P register was limited to 15 bits before rollover and the operand address was also limited to 15 bits. In expanded addressing mode the P Register was lengthened to 18 bits and operand address generation used the upper 2 bits of y to address 3 Extension Registers which concatonated a 5-bit constant to the lower 13 bits of y resulting in an 18 bit address. This was referred to as the 262K address range. All of the production CP-890's were built with only 32K of memory. The 1230MTC delivered to the Air Force was a repackaged CP-890 but added an additional memory chassis for a total of 65K. The ARTS-III IOP used the same address generation architecture and most of the instruction set of the CP-890 (no floating point). They eventually did incorporate all 262K of memory and may have added more. [rae]
The Navy never, as far as I know, seriously explored adding more memory into the basic CP-890 box. We were aware of the fact that they did roll in software processes as they were needed but had made the decision to maintain the tape units rather than adding memory to the CP-890. [rae]
The mechanical shape of this unit was unique to enable lowering through submarine hatches. Although the extension registers gave the design the capability to access 131k of memory and the chassis could hold 65k, the units were delivered with only 32k words. This unit's processing power and connected sensors facilitated submarine navigation under the polar ice cap. [lab]
The photo at the right was provided by Jack Lavers. Thanks to Tom Eykyn for identifying this CP-890 production management team of Jim Knox, Victor Patriaz, Ray Dombeck, Jack Lavers, Jerry Burnett, Myself, Chuck Mueller, Dave Young. [lab]
I should note here that when I did the Architecture for the Memory Processor to replace the CP-890 I provided 24 bits of addressing. We delivered two 2 processors and a common memory rack containing 8 MB in each of the Trident Memory Processors. Two processors could easily share a common memory due to the presence of extremely large Cache Memories in front of both processors. Commercial processors at the time were only using level 1 caches (level 2 was not here yet) of 256 bytes. Each Memory processor CPU had 256K bytes. That was all done in the early 80's. [rae]
CP-890 Information:
Customer - US Navy Environment - Submarine First Delivery - October 1967 Quantity built = 197
Vol/Ft3 = 13 Wt/Lbs = 725 Pwr/Wts = 2150 Mem/Cyc = 1.8 usec Mem/Cap = 131k
I/O rate = 555kw/sec I/O channels - 16 duplex; -3v or -15v
3.11 CP-901 - Univac Type #1830A.
A design team led by supervisor, Ken Oehlers, began development of the CP-901 (1830A) in April 1966. This unit was to be the core of the AN/ASQ-114 Anti-Submarine Warfare (ASW) Lockheed P3-C aircraft. 
Others that I recall were Finley McLeod (department manager), George Kydd (I/O logic), John Bonnes (arithmetic), Ralph Mattie and Al Schwartz (memory), John Grape and LeRoy Vick (power supply), Dennis Paulinski (wire tabs), and me (PC board layout, mfg interface, and test software support.) Field Service Engineer, Jack Anderson, and Lowell flew on a P3 to deliver the first unit to the Naval Air Development Center in Johnsville, PA. This design had several innovations:
- A 512 word bootstrap (core-rope) program had a designed-in self test program to test basic arithmetic, memory, and I/O functions before initiating program load from either a magnetic tape or drum unit.
- It was the first to use a flat-pack integrated circuit (p/n 7901000 and 7901001) on a conduction cooled printed circuit card. Heat was conducted from the chip to the under chip heat sink to a 'T' bar at the top of the printed circuit card. A honeycombed heat exchanger pushed down on rows of these T-bars to transfer heat from the T-bars to air.
- The 16k word core memory chassis had three access ports. When the main frame was configured with three or four memory chassis, the logic design would access up to three memory banks simultaneously - an I/O transfer, an operand fetch or store, and the next instruction fetch.
- A set of sixteen 6-bit page registers to extend the memory addressing from the basic 32k words to 131k words plus a memory protect feature.
- A power failure detection mechanism to interrupt the program sequence so that critical data could be stored into core memory thereby facilitating quick mission resumption when the power returned to normal.
The first CP-901 was delivered to Johnsville, PA in September 1967 for software development. With S/N 499 delivery in 1993 this design was the longest production run of any other UNIVAC equipment! It is being phased out of operation by the CP-2044, an embedded emulation system whose development began in the early '90s. Although designed to address 131k words, the first 50 units were delivered with three memory chassis for 48k total. A fourth chassis was added to all units in the early '70s and in continuing production for a 64k operational system configuration. [lab]
AN/ASQ114 (CP-901) Information:
Customer - NAVAIR Environment - Airborne First Delivery - September 1967 Quantity built = 499
Vol/Ft3 = 6.9 Wt/Lbs = ~380 Pwr/Wts = 1400 Mem/Cyc = 2 usec Mem/Cap = 65k
I/O rate = 167 kw/sec I/O channels 16 duplexed, +3v
3.12 1830B German Navy Computer -
In the late 60's the German Navy began development of a Fast Patrol Boat (FPB) for coastal defense. Hollandse Signaal Apparatan (HSA) [the military division of Phillips Global-Technique] and Univac submitted bids. The German Navy accepted the UNIVAC bid because they were quite happy with the performance and reliability of their 642B computers plus German sailors were familiar with the software development tools. Univac had proposed a shipboard version of the CP-901. There were four innovations for the first delivery in September 1970:
- Create a ship board cabinet to hold the airborne chassis.
- Adapt an I/O chassis using AN/UYK-7 printed circuit cards to provide the Mil-Std-1397 type A and type B interfaces (the CP-901 only had Type-C ANEW I/O channel.) We also used the UYK-7 'single window' core stacks for better sense amp operation.
- Adapt a type C channel to work as an External Specified Index with the HSA 24 bit I/O bus for their peripherals, and
- Medium Scale Integration (MSI) integrated circuit real-time clock and count-down clock to give the system response control at 100 kilo-hertz versus the 1 kilo-hertz real time clock used by previous 30 bit computers. [lab]
In the mid '70s the US Navy began development of a Hydrofoil ship at Boeing. They needed a small ships combat system so they asked the German Navy for an adaptation of the FPB system. The first ship, the Pegasus, received an 1830B, a Telefunken display, an HSA radar, and an Italian 88mm twin barreled anti-aircraft gun. As the Navy started testing the system outside of Port Hueneme CA, the system went dead when the gun was fired. The Navy called St. Paul 
- Lowell was dispatched to help Bob Herbster (Field Service). The next day, again at the Pacific firing range a plane flew over towing a target drone, the ship fired, the system went dead. I noted that both the program fault light and the power fault light were lit. Then I asked to see the power recovery program - there was none thus the reason for the program fault light. Half an hour later I had written a short power recovery program, plugged it into memory in machine code, and restarted the system. The drone towing plane came back, the gun fired, the display system blinked, then kept tracking the drone. The power fault light was lit on the computer but the program fault light was not. The Navy was delighted - the Bob and I investigated the power fault and found that the 400 HZ generator mounted on the aft deck wasn't secured. When the gun was fired the generator had jerked side to side causing it to briefly lose its output. An innovation of the CP-901 carried forward to the 1830B was detection of an impending power failure. If the input power dropped below a specified level, a power fault interrupt was sent to the processor. There was sufficient residual power stored in the power supply to allow a couple more seconds of operation. A power fault program could quickly store status and critical data, then upon recovery of power could restart where it left off. The Navy built five more Hydro-foil ships - used an upgraded systems with their AN/UYK-7 standard computer. [lab]
1830B Information:
Customer - German Navy Environment - Shipboard First Delivery - September 1970 Quantity built = 85
Vol/Ft3 = 10 Wt/Lbs = 481 Pwr/Wts = 1500 Mem/Cyc = 2 usec Mem/Cap = 65k
I/O rate = 167 kw/sec I/O channels 16 duplexed; -3v, -15v, +3.5v
3.13 AN/UYK-8 -
The AN/UYK-8 was another update to the Marine Tactical Data System. This was part of their AN/AYS-20 system. It used the same cooling heat exchanger and card designs as were used in the CP-901. Bob Oulicky was the engineering manager of this project. The 16k word core memory chassis had four 4k word stacks. The support frame for for each word plane of the stack used a single window compared to the two window design of the CP-901. This moved the cores a bit closer together allowing shorter x & y drive lines as well as the inhibit and sense line being shorter. This allowed faster cycle times. The memory stacks had 32 coreplanes to provide a parity bit for each half word. These memory stacks were also used in the AN/UYK-7 and in the 1830B. This was a dual processor capable machine. [lab]
AN/UYK-8 Information:
Customer - USMC Environment - Shelter First Delivery - January 1969 Quantity built = 22
Vol/Ft3 = 10.4 Wt/Lbs = 530 Pwr/Wts = 2000 Mem/Cyc = 1.5 Mem/Cap = 48k
I/O rate = 500 kw/sec I/O channels 16 duplex; -15v, -3v, or =3v
3.14 UNIVAC TYPE #1530 -
MTC (Mobile Tactical Computer) was developed for the U.S. Air Force. Generally called the 1230 MTC because it performed many of the same system functions as the 1230 developed earlier for NASA. It used many of the CP-890 printed circuit cards - but was a dual processor packed into a single cabinet. See the Systems, Missile page for more about this system computer. [lab]
By Don Neuman - We only sold one 1530 and that was to JPL in Pasadena. That machine was in a 1230 mTc cabinet but it was a single processor, single I/O with 64k of memory. (Both memory drawers were used) When we closed the Kodiak tracking station, JPL picked up the 1230 mTc and used it to process pictures from the Galileo deep space probe.
Marketing thought that the JPL image processing algorithms could be used to start a new business line. They set up a lab using a 1616 computer and a digital scanner to process mammograms. The guys had a good time looking at their work but technology overtook us and cheaper, better, faster image enhancement systems came on the market before we finished the project.
The processor #1 of serial #1 1230 mTc had so many hand wraps that it was intermittent. The Air Force requested us to build a new processor chassis (Fixed price), and then transfer all of the cards and power supplies form the old unit to the new chassis. Manufacturing priced this effort by just escalating the original cost to current dollars. When we built the chassis, there was a $250,000 over run. The price of gold had gone up from $32 per oz, to $800 per oz and nobody had thought of this. (There was a lot of gold in them there machines.)
Later in the program, the Air Force task us with replacing the 64k of core memory with 256K of semiconductor memory. The new memory was triple redundant with two parity bits in a new cabinet (see picture). We removed the core memory and taped the air vents shut. Later the computer operators complained about the noise level caused by the 400 Hz blowers. I got to travel to all of the sites to analyze this noise. (What a boondoggle.) My solution was a hood lined with acoustic foam. (See picture - right.)
The 1230 mTc did have hardware-floating point. The mathematicians came to me and said that the computer was wrong sometimes. After a lot of analyzing, I found a runt pulse in the mantissa rounding logic. Sometimes it would round and sometimes it would not round. This small error affected the orbit of the satellite we were working with.
1530 MTC Information:
Vol/Ft3 = 12 Wt/Lbs = 800 Pwr/Wts = 4500 Mem/Cyc = 1 usec Mem/Cap = 262k
I/O rate = 555 kw/sec I/O channels - 16 duplexed. First delivery, February 1968.
3.15 ARTS III IOP -
Engineers from the CP-890, CP-901, and AN/UYK-8 design teams transitioned onto yet another 30-bit ISA project, i.e. creating a faster performance multi-processor for Air Traffic Control applications. The resulting Input Output Processor in several multiprocessor configurations was installed at 64 major airports for the Automated Radar Tower System. These ARTS III processors replaced the Arts I and Arts II 1218 processors. J ohn Bonnes was one of the IOP design engineers. [lab]
ARTS III Input Output Processor (IOP) Information:
Customer - FAA Environment - Ops Room First Delivery - April 1969 Quantity built = 110
Vol/Ft3 = configuration dependent Wt/Lbs = configuration dependent Pwr/Wts = configuration dependent
Mem/Cyc = 750 nanosec Mem/Cap =
I/O rate = I/O channels 16 duplexed, +3v with a shorter acknowledge pulse that the ANEW +3 v interface.
3.16 ARTS III IOP Enhancements:
These were multiprocessor systems needed to handle the traffic at five airports in the New York City area. The hardware system could interconnect up to eight processors.
VIP Page 52 updated Tuesday, June 03, 2008